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Engineering |
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Henry
Samueli School of Engineering and Applied Science |
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Interdisciplinary Research Team Leads Nanoscale Research in New Materials
for Silicon Chips
Professors Jenn-Ming Yang, King-Ning Tu,
Nasr Ghoniem, and Nicholas Kioussis. |
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The integrated circuits in personal computers, cellular phones, electronic games and other consumer electronics have become significantly smaller in the last decade – some have nearly a billion transistors per chip. As the number of transistors on a single tiny chip increases, the materials used in the transistors also must be scaled down in size, and researchers are finding that these elements operate very differently at the nanoscale.
Funded by a $1.3 million grant from the National Science Foundation, researchers at the UCLA Henry Samueli School of Engineering and Applied Science are developing methods to strengthen and improve materials used for interconnect and packaging components for high-tech chips.
“It is a very realistic project directly linked to devices and practical applications,” explains UCLA materials scientist King-Ning
Tu. “It’s not five or 10 years down the road; we’re taking the next logical step.”
SEM image of
an eight-level copper interconnect structure. (Courtesy
of Dr. Jeffrey Su, Institute of Microelectronics,
Singapore.) |
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Tu is partnering with mechanical and aerospace engineering professor Nasr
Ghoniem, who specializes in advanced computer simulations, materials science and engineering professor Jenn-Ming
Yang, and Nicholas Kioussis, a professor of physics at California State University, Northridge on three primary project goals: to strengthen copper at the nanoscale, improve its reliability, and create a better insulation material.
The team is working to improve the mechanical properties of copper, which already has very good electrical properties. Copper is commonly used for interconnect wires in transistors, which are only just a fraction of the width of a human hair. When reduced to only 50 nanometers in width, however, gravity causes the copper to sag, creating interference between the wires.
Nano-twinned copper, which is specially treated to add patterned irregularities, is 10 times stronger than untreated copper, while losing none of its electrical conductivity – making
it an ideal material for silicon interconnects. To prevent electromigration in
the revolutionary material, the researchers will look to advanced computer simulations
to explore its properties.
“We are concerned with the reliability of the materials,” says Tu. “We want to ensure that the technology is stable and will have a shelf life of five to 10 years.”
The high currents running through the wires can shift atoms in the copper, changing
the atomic structure and possibly creating a void or short. The simulations devised
by Ghoniem - who holds a joint appointment in materials science and engineering
- and
Kioussis
will
help
determine
the
electromigration
tendencies
of nano-twinned copper and prevent future equipment failures.
To further reduce interference between the wires, Tu and his colleagues are building on research begun last year to develop hollow glass nanoparticles that can serve as the dielectric – or insulation material. Current methods of creating air bubbles in glass leave open channels, which can lead to corrosion and flaws in the transistors. The hollow nanocrystals created by Tu and his colleagues allow air to be introduced into glass –improving its attributes as a dielectric – without any undesired characteristics.
The nano-twinned copper and hollow glass nanocrystals both have direct applications to future nanoelectronics. A partnership with Intel will help speed the technology’s transition from lab to marketplace.
For media inquiries, please contact Melissa Abraham
(mabraham@support.ucla.edu or 310/206-0540.)
- Marlys Amundson
08.19.05
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2004 UCLA |
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